DK-DEV-5SGXEA7N【PDF 33/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51003

2013.05.06

M20K

MLAB

Embedded Memory Clocking Modes

2-11

Memory Mode

Shift-register

Support

Yes

Support

Yes

Description

You can use the memory blocks as a shift-register block to save

logic cells and routing resources.

This is useful in DSP applications that require local data storage

such as finite impulse response (FIR) filters, pseudo-random

number generators, multi-channel filtering, and auto- and cross-

correlation functions. Traditionally, the local data storage is

implemented with standard flip-flops that exhaust many logic

cells for large shift registers.

The input data width (w), the length of the taps (m), and the

number of taps (n) determine the size of a shift register

(w × m × n). You can cascade memory blocks to implement larger

shift registers.

ROM

Yes

Yes

You can use the memory blocks as ROM.

? Initialize the ROM contents of the memory blocks using a .mif

or .hex .

? The address lines of the ROM are registered on M20K blocks

but can be unregistered on MLABs.

? The outputs can be registered or unregistered.

? The output registers can be asynchronously cleared.

? The ROM read operation is identical to the read operation in

the single-port RAM configuration.

FIFO

Yes

Yes

You can use the memory blocks as FIFO buffers. Use the SCFIFO

and DCFIFO megafunctions to implement single- and dual-clock

asynchronous FIFO buffers in your design.

For designs with many small and shallow FIFO buffers, the

MLABs are ideal for the FIFO mode. However, the MLABs do

not support mixed-width FIFO mode.

Related Information

? Internal Memory (RAM and ROM) User Guide

Provides more information memory modes.

? RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide

Provides more information about implementing the shift register mode.

? SCFIFO and DCFIFO Megafunctions User Guide

Provides more information about implementing FIFO buffers.

Embedded Memory Clocking Modes

This section describes the clocking modes for the Stratix V memory blocks.

Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the

memory block input registers during read or write operations.

Embedded Memory Blocks in Stratix V Devices

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